The present invention relates to a semiconductor storage device comprising a floating gate EEPROM (electrically erasable and programmable read-only memory) and a method of manufacturing the same.
An EPROM (erasable and programmable read-only memory) having a floating gate structure has been conventionally well known as a nonvolatile memory. In this EPROM, a floating gate electrode is disposed on a channel region sandwiched between a source region and a drain region formed in a semiconductor substrate with a gate insulating film sandwiched between the floating gate electrode and the channel region, and a control gate electrode is disposed on the floating gate electrode with an interlayer insulating film sandwiched therebetween. In a data write operation of this EPROM, hot electrons are generated in the channel region in the vicinity of the drain region in the semiconductor substrate by allowing a current to flow through the channel region under application of a high voltage between the drain region and the control gate electrode, so that a data can be written by acceleratingly injecting the hot electrons into the floating gate electrode.
On the other hand, a data erase operation of the EPROM is conventionally conducted through UV irradiation, but recently, a data erase operation by utilizing a phenomenon that electrons can tunnel through the gate insulating film formed in a small thickness has been proposed. In this data erase operation, a data is electrically erased by releasing electrons from the floating gate electrode to the source region, the drain region or the channel region, namely, toward the semiconductor substrate, by utilizing the phenomenon.
Moreover, a memory cell structure in which a data is electrically erased by using an independently formed erase electrode instead of releasing electrons toward the semiconductor substrate has recently been proposed (for example, in Japanese Laid-Open Patent Publication No. 4-340767). In this memory cell structure using the erase gate electrode, a tunneling insulating film is disposed between the erase gate electrode and the floating gate electrode, so that a data can be erased by allowing electrons to tunnel from the floating gate electrode to the erase gate electrode under application of an erase voltage to the erase gate electrode.
On the other hand, there are recently increasing demands for improvement in refinement, integration and performance of semiconductor devices, and hence, further refinement and higher performance are also earnestly required of the above-described electrically erasable floating gate EEPROM.
Now, an example of the conventional floating gate semiconductor storage device equipped with an erase gate electrode will be described with reference to FIGS. 19 and 20(a) through 20(c). FIG. 19 is a plan view for showing the structure of a memory part of the conventional semiconductor storage device, and FIGS. 20(a) through 20(c) are sectional views thereof taken on lines XXaxe2x80x94XXa, XXbxe2x80x94XXb and XXcxe2x80x94XXc of FIG. 19.
As is shown in FIGS. 19 and 20(a) through 20(c), the conventional semiconductor storage device includes first and second diffusion layers 102a and 102b serving as source/drain regions formed by introducing an impurity into a Si substrate 101; an isolation insulating film 103 of a silicon oxide film deposited on the Si substrate 101; a gate insulating film 104 of a silicon oxide film; a floating gate electrode 105 of a polysilicon film; a control gate electrode 106 of a polysilicon film; a capacitor dielectric film 107 of a silicon oxide film disposed between the floating gate electrode 105 and the control gate electrode 106; a tunneling insulating film 111 of a thin silicon oxide film formed on the side face of the floating gate electrode 105; an erase gate electrode 109 of a 152 polysilicon film opposing the side face of the floating gate electrode 105 with the tunneling insulating film 111 sandwiched therebetween; a gate upper insulating film 112 of a silicon oxide film formed on the control gate electrode 106; an insulator sidewall 113 formed on the side faces of the capacitor dielectric film 107, the control gate electrode 106 and the gate upper insulating film 112; an interlayer insulating film 114 of a silicon oxide film deposited in a large thickness; first and second contact holes 115a and 115b formed in the interlayer insulating film 114 so as to respectively reach the first and second diffusion layers 102a and 102b; and a metal interconnect layer 116 formed so as to fill the first and second contact holes 115a and 115b and partially cover the interlayer insulating film 114.
In this structure of the conventional semiconductor storage device, however, as the design rule is further refined to a half micron or less, in a section where the first and second contact holes 115a and 115b appear as in FIG. 20(c), a distance between the first and second diffusion layers 102a and 102b serving as the source/drain regions becomes too small to easily cause a source-drain leakage. Accordingly, the lateral dimension of the first and second diffusion layers 102a and 102b shown in FIG. 20(b) is also restricted. However, in order to form the first and second contact holes 115a and 115b accurately on the first and second diffusion layers 102a and 102b, it is necessary to secure an overlap margin for lithography in consideration of variation caused in the manufacturing procedures. Therefore, in order to form the first and second contact holes 115a and 115b accurately on the first and second diffusion layers 102a and 102b having a small lateral dimension in FIG. 20(b), the diameter of the first and second contact holes 115a and 115b should be further reduced. In other words, the lateral dimension of the first and second contact holes 115a and 115b in the section shown in FIG. 20(c) should be unavoidably reduced in order to prevent the source-drain leakage.
When the diameter of the first and second contact holes 115a and 115b is further reduced, however, the aspect ratio of the first and second contact holes 115a and 115b becomes so large that various other problems can be caused because of the structure in which the floating gate electrode 105, the control gate electrode 106 and the erase gate electrode 109 are stacked. Specifically, a microloading phenomenon can be caused in dry etching for forming the first and second contact holes 115a and 115b, and connection failure derived from degradation of the coverage of a metal material can be caused in deposition of the metal material for forming the metal interconnect layer 116 within the first and second contact holes 115a and 115b. 
An object of the invention is providing a floating gate semiconductor storage device that can be refined while preventing source-drain leakage by providing means for reducing an aspect ratio of a contact hole filled in a member in contact with a diffusion layer formed in a semiconductor substrate, and a method of manufacturing the same.
The semiconductor storage device of this invention comprises a semiconductor substrate; first and second diffusion layers working as source/drain regions formed by introducing an impurity into the semiconductor substrate; an isolation insulating film formed on the semiconductor substrate in an area including a part of the first diffusion layer and a part of the second diffusion layer; a gate insulating film formed on the semiconductor substrate in an area between the first and second diffusion layers; a floating gate electrode formed on the gate insulating film; a control gate electrode formed on the floating gate electrode; a capacitor dielectric film disposed between the floating gate electrode and the control gate electrode; a tunneling insulating film formed in contact with a side face of the floating gate electrode; an erase gate electrode opposing the side face of the floating gate electrode with the tunneling insulating film sandwiched therebetween; first and second contact members filled in two lower contact holes formed in the isolation insulating film to be in contact with the first and second diffusion layers; an interlayer insulating film deposited over the first and second contact members and the control gate electrode; and an interconnect layer filled in two upper contact holes formed in the interlayer insulating film to be in contact with the first and second contact members.
In this manner, the depth of the upper contact holes can be reduced correspondingly to the height of the first and second contact members filled in the lower contact holes formed in the isolation insulating film. Accordingly, when it is necessary to reduce the diameter of the upper contact holes, increase of the aspect ratio of the upper contact holes can be prevented. In particular, in a floating gate semiconductor storage device equipped with an erase gate electrode, the interlayer insulating film tends to become thicker because the level difference between the uppermost portion and the lowermost portion of the substrate underlying the interlayer insulating film is large, but even in such a case, the increase of the aspect ratio can be suppressed. As a result, the floating gate semiconductor storage device can be very refined while preventing leakage between the source/drain regions.
In the semiconductor storage device, when each of the contact members partially covers the interlayer insulating film so as to work as an extension electrode, the lateral dimension of the upper contact holes can be enlarged in accordance with increase of the upper area of the contact member, and hence, the aspect ratio of the upper contact holes can be reduced.
In the semiconductor storage device, when the isolation insulating film is made from an insulating film deposited by CVD, the increase of the aspect ratio of the contact hole can be suppressed against the further increased level difference on the substrate underlying the interlayer insulating film while realizing a floating gate semiconductor storage device suitable to refinement.
In the semiconductor storage device, when the contact members are made from the same material as any of the floating gate electrode, the control gate electrode and the erase gate electrode, manufacturing procedures can be simplified, resulting in reducing the manufacturing cost.
The contact members are preferably made from at least one of a refractory metal and polysilicon.
In the semiconductor storage device, when at least a lower portion of each of the contact members is made from a non-doped semiconductor, occurrence of leakage between the first and second diffusion layers can be suppressed.
When the semiconductor storage device further comprises an insulator sidewall sandwiched between each of the contact members and the side face of each of the lower contact holes, diffusion of an impurity from the first and second diffusion layers into the semiconductor substrate can be suppressed, resulting in more effectively suppressing the occurrence of leakage between the first and second diffusion layers.
The method of manufacturing a semiconductor storage device of this invention comprises the steps of (a) forming first and second diffusion layers working as source/drain regions in a semiconductor substrate; (b) forming an insulating film for isolation on an area including a part of the first diffusion layer and a part of the second diffusion layer after the step (a); (c) forming an isolation insulating film by patterning the insulating film for isolation; (d) forming first and second lower contact holes respectively reaching the first and second diffusion layers by patterning the insulating film for isolation after, before or simultaneously with the step (c); (e) forming a first insulating film on the semiconductor substrate in an area surrounded with the isolation insulating film after the step (c); (f) forming a first conductive film, a second insulating film, a second conductive film and a third insulating film successively on the first insulating film after the step (e); (g) forming a gate upper insulating film, a control gate electrode and a capacitor dielectric film by patterning the third insulating film, the second conductive film and the second insulating film after the step (f); (h) forming an insulator sidewall on side faces of the capacitor dielectric film, the control gate electrode and the gate upper insulating film after the step (g); (i) forming a floating gate electrode by removing the first conductive film through etching by using the insulator sidewall as a mask after the step (h); (j) forming a tunneling insulating film on a side face of the floating gate electrode after the step (i); (k) forming an erase gate electrode opposing the floating gate electrode with the tunneling insulating film sandwiched therebetween after the step (j); and (l) forming contact members filled in the lower contact holes.
By this method, the semiconductor storage device capable of exhibiting the aforementioned effect can be easily manufactured.
When the insulating film for isolation is formed by CVD in the step (b), the semiconductor storage device can attain a structure suitable to refinement.
The step (l) and the step (k) can be simultaneously ok carried out and the contact members and the erase gate electrode can be simultaneously formed by forming and patterning a third conductive film in the step (l).
Furthermore, the step (d) can be carried out before the step (e), the second conductive film and the third insulating film can be formed on the lower contact holes in the step (f), and the step (l) and the step (g) can be simultaneously carried out.
When the method of manufacturing a semiconductor storage device further comprises, before the step (f), a step of forming an insulator sidewall on side faces of the first and second lower contact holes, diffusion of an impurity from the first and second contact members into the semiconductor substrate can be suppressed.
When the step (d) is carried out before the step (c), the first and second lower contact holes can be formed on the insulating film for forming an isolation having a flat surface, and hence, each lower contact hole can be refined to a resolution limit in photolithography.
The contact members can be made from a stacked film including a refractory metal film and a semiconductor film in the step (l).
The contact members can be made from a stacked film including two or more semiconductor films having different impurity concentrations in the step (l).
In particular, when the contact members are formed in the step (l) by successively depositing a non-doped polysilicon film and an amorphous silicon film on the semiconductor substrate, implanting impurity ions into the amorphous silicon film, and patterning the polysilicon film and the amorphous silicon film, the impurity doped in the upper portions of the first and second contact members can be definitely prevented from diffusing into regions larger than the first and second diffusion layers.